IBM has disclosed a new semiconductor architecture that it says can produce chips with a transistor density equivalent to a 0.7-nanometre process node, roughly twice the density of its 2nm design unveiled in 2021. In internal testing, the prototype delivered up to 50 percent higher processing performance or 70 percent greater energy efficiency than the company’s 2nm reference chips, according to statements from IBM Research. The technology remains at the research stage and is not yet ready for industrial fabrication; the company estimates a path to mass production within five years.

The advance rests on a three-dimensional transistor layout IBM calls NanoStack. Instead of arranging transistors in a single planar layer, the design stacks multiple layers of transistors vertically, allowing nearly 100 billion of them to fit on a chip the size of a fingernail. IBM executives said the same stacking approach can be applied to CPU and GPU logic chips as well as to SRAM memory, where it yielded a 40 percent performance improvement—a gain the company described as unseen in decades. The architecture, they added, could extend the miniaturisation roadmap toward 0.1nm, or one angstrom, around 2040.

Viewed from the semiconductor-manufacturing hubs of East Asia, the announcement adds a new dimension to an already intensifying race. Taiwan’s TSMC, the world’s largest contract chipmaker, began volume production of 2nm chips in late 2025 and has signalled plans to move to 1.4nm by 2028. Japan’s Rapidus, which licenses IBM’s 2nm technology, aims to start large-scale output in the second half of 2027. Intel, meanwhile, recently moved its 1.8nm-class 18A process into risk production. IBM does not operate its own advanced fabrication plants; it licenses its chip designs to manufacturers. The company said it is currently focused on scaling its 2nm node with partners and has not named a manufacturing partner for the 0.7nm technology.

The disclosure lands as data-centre operators and chip designers confront the ballooning energy demands of artificial intelligence workloads. IBM’s projected efficiency gains, if realised in commercial silicon, would address a critical constraint for the industry. The next factual milestone to watch is the ramp-up of 2nm production at Rapidus in 2027, which will test the commercial viability of the underlying design philosophy that the new NanoStack architecture extends.